1. Field of the Invention
The present invention relates to substrates for use in integrated circuits and more particularly to a dielectrically isolated substrate of a bonding type having squared and maximized island regions. The invention further relates to a process for producing such a unique substrate.
2. Description of the Prior Art
In fabricating those substrates intended for use in integrated circuits for semiconductor devices, a p-n junction isolation technique using diffusion layers has been widely employed to isolate the individual elements of the substrate from each other. This isolation diffusion techniques is not only relatively simple in steps but easy in process control. However, it is susceptible to excessive isolation capacitances and poor high frequency characteristics and hence low operating speed in circuits. Alternatively, a dielectric isolation technique using dielectric layers has been proposed which is reputed as fully acceptable in parasitic capacitances and breakdown characteristics.
A dielectrically isolated substrate of a bonding type is known to be a substrate obtained by the last-mentioned dielectric isolation technique as disclosed for instance in Japanese Patent Laid-Open Publication No. 62-229855. This conventional substrate is produced as will be hereunder described with reference to FIGS. 13(a) through 13(j).
An N.sup.+ dopant such as of antimony (Sb), arsenic (Ar) or the like is buried and diffused to a mirror polished surface of a single crystal silicon substrate or bond substrate 2 with a (100) plane as the main crystal plane as shown in FIG. 13(a), followed by formation of a dielectric film 4 of silicon dioxide (SiO.sub.z) over the surface of the bond substrate 2 as by thermal oxidation. The bond substrate 2 is contacted with another substrate or base substrate 6 with their mirror polished surface opposed to each other and thereafter bonded together into an integral structure 8 at above 200.degree. C. as depicted in FIG. 13(b).
The substrate 2 of the structure 8 is ground and polished to a thickness of 30 to 50 .mu.m [FIG. 13(c)], followed by formation of oxide film 10 of nearly 0.6 .mu.m in thickness, for subsequent photo-lithography, over an outer surface of the substrate 2 as through thermal oxidation [FIG. 13(d)]. Small openings or windows 12 are formed photo-lithographically selectively in the oxide film 10 according to an isolation mask pattern [FIG. 13(e)], whereby the surface of the substrate 2 is anisotropically etched through the windows 12 into V-shaped isolation grooves or moats 14 so that island regions 16 are formed on both sides of each of the moats 14 [FIG. 13(f)]. An isolation oxide film 18 is then disposed in a thickness of about 2 .mu.m and over both the islands and the moats [FIG. 13(g)]. Deposited over the oxide film 18 is a polycrystalline silicon layer 20 in a thickness of 40 to 80 .mu.m [FIG. 13(h)], whereupon lapping is effected from toward the silicon layer 20 with the oxide film 18 being used as a stopper layer [FIG. 13(i)]. A dielectrically isolated substrate D1 is obtained by finally removing the oxide film 18 [FIGS. 13(j) and 14].
The above substrate of the prior art derivable from a single crystal silicon substrate with a (100) plane as the main crystal plane, is disadvantageous in that it is necessarily narrow in island area due to the corresponding V-shaped isolation moats. The island area becomes smaller as the substrate increases in thickness.